This invention relates to a new construction of a read only memory (referred to as ROM) which is constructed by use of a static induction transistor (referred to as SIT) and can realize a high packing density.
Recently, a static induction transistor logic device (referred to as SITL) has been proposed as a logic element which operates with low power dissipation and has a wide frequency range. The operations of the SITL and the SIT will be described in conjunction with FIGS. 1 and 2. FIG. 1(a) illustrates a sectional view of a SITL device. In FIG. 1(a), reference 5 is a N.sup.+ substrate which acts as a base electrode of a PNP transistor and a source of a SIT, 6 is a N.sup.- epitaxial layer which has a surface impurity density of less than 1.times.10.sup.14 [atoms/cm.sup.3 ] and acts as a base of the PNP transistor and a channel of the SIT, 7 is a P.sup.+ region which acts as an emitter of the PNP transistor, 8 is a P.sup.+ region which acts as a collector of the PNP transistor and a gate of the SIT, 9 is a N.sup.+ region acting as a drain of the SIT, 10 is an insulation layer such as SiO.sub.2, 1 is an injector electrode, 2 is a gate electrode, 3 is a source electrode and 4 is the drain electrode. FIG. 1(b) is a equivalent circuit diagram of the SITL comprised of a PNP transistor T.sub.1 and a SITT.sub.2.
An injector voltage of more than 0.4 volts is normally applied to the injector electrode of the SITL. As a result, a collector current of the PNP transistor T.sub.1 flows out a previous stage through a gate electrode 2 when the gate electrode 2 is at ground level. At this time, as shown by line a of FIG. 2(a), a potential barrier for electrons moving from the source 3 to the drain 4 is high in the adjacent portion enclosed with the gate 8, and there are extremely few electrons moving from the source 5 to the drain 9 even if the voltage is impressed to the drain electrode 4 as shown by the curve b. Therefore, the SITT.sub.2 is turned off so that the level of the drain electrode 4 is closed to an injector voltage due to the load of the subsequent stage. On the other hand, since the collector current of the PNP transistor T.sub.1 flows into the gate 8 of the SITT.sub.2 when the previous stage of the SITL is turned off, the voltage potential at the gate 8 is increased to close the injector voltage. At this time, since the above mentioned potential barrier becomes low as shown by the curve a in FIG. 2B, large amounts of electrons are moved from the source 5 to the drain 9. Considering the above discription, it will be understood that the drain current of the SIT exponentially changes in accordance with the gate voltage. FIG. 3 illustrates a drain-source voltage to drain-source current characteristic for a SIT. From FIG. 3, it is understood that the drain-source current exponentially changes in accordance with the gate voltage.
In such a SITL, a few fJ can be attained in the electric characteristic and the power delay product; and it is recognized that such a SITL is an excellent circuit element. However, a SIT ROM which is able to enlarge its application has not been presented yet so that the SITL has not come into wide use for the present.